Course provided by Udemy

Study type: Online

Starts: Anytime

Price: See latest price on Udemy


Twelve lectures, starting from the basics of VHDL, including the entity, architecture, and process.  Explanations of the difference in sequential and concurrent VHDL.  Discussions of good synchronous design methodology.  Demonstrations on how to use the Altera Modelsim and Xilinx Vivado simulators. Six lab projects for hands-on experience, with the instructor showing how he would have done each lab.

Expected Outcomes

  1. Practical FPGA and ASIC RTL design using VHDL